1. Field of the Invention
This invention relates to a circuit and a method for reconfiguring fuse sets for memory cell array redundancy repair.
More particularly this invention relates to the use of fuse sets and spare row and column lines in the memory array to repair memory cell defects.
2. Description of Related Art
FIG. 1 shows a prior art memory block diagram. The memory array 130 is accessed via the regular row decoder and driver block 120, and via the regular column decoder and driver block 150. The row address buffer 110 drives both the regular row decoder/driver 120 and the redundant row driver and fuse set 160. The output of the redundant row driver and fuse set 160 is a ‘Hit’ output signal 190. This ‘Hit’ 190 output indicates that the row address 180 equals any address in the redundant row driver and fuse set 160.
Similarly, the column address buffer 170 drives both the regular column decoder/driver 150 and the redundant column driver and fuse set 140. The output of the redundant column driver and fuse set 140 is a ‘Hit’ output signal 125. This ‘Hit’ 125 output indicates that the column address 115 equals any address in the redundant column driver and fuse set 140.
U.S. Pat. No. 5,430,679 (Hiltebeitel, et al.) “Flexible Redundancy Architecture and Fuse Download Scheme” describes a fuse download system for programming decoders for redundancy. The fuse sets can be dynamically assigned on an any-for-any basis.
U.S. Pat. No. 5,646,896 (Pinkham) “Memory Device with Reduced Number of Fuses” discloses a memory device with a reduced number of fuses. Fuse programming circuits are shared between memories.
U.S. Pat. No. 6,018,811 (Merritt) “Layout for Semiconductor Memory Device Wherein Intercoupling Lines are Shared by Two Sets of Fuse Banks and Two Sets of Redundant Elements Not Simultaneously Active” discloses a circuit where intercoupling lines are shared by two banks of fuses.”